This invention relates to nonvolatile semiconductor memory devices and, more particularly, to flash electrically erasable, programmable, read-only memories (flash EPROMs) having floating-gate-type memory cells and, more particularly, to a method of making such devices on a chip while at the same time making digital control circuitry.
An array structure using buried diffusion wells (tanks) is described in U.S. Pat. No. 5,411,908 issued May 2, 1995, and entitled xe2x80x9cFLASH EEPROM ARRAY WITH P-TANK INSULATED FROM SUBSTRATE BY DEEP N-TANKxe2x80x9d. That patent is assigned to Texas Instruments Incorporated.
The prior-art includes programming and erasing floating-gate memory cells by Fowler-Nordheim tunneling. During flash erasure of floating-gate cells by Fowler-Nordheim tunnelling, the substrate and control gates (wordlines) of each cell are typically connected to 0V, the sources (source lines) of each cell are connected to a positive voltage of perhaps +10V to +15V, and the drains (bitlines) are allowed to float (connected to a high impedance). In the prior-art, tunnelling areas are usually formed between the floating gate and a double-diffused source extending under the floating gate, but separated from the floating gate by a thin gate insulator. In other cases, tunneling occurs in a window having a thin insulator formed at or near the source.
When using a double-diffused tunnel, the source of each cell is typically formed by an arsenic doping at the same time the drain is doped, followed by a separate mask and phosphorus doping steps, followed by a driving anneal step that causes the phosphorus of the source diffusion to expand under the floating gate to form a tunnelling region. As a result, the floating gate must have sufficient length that the phosphorus diffusion of the source does not reach through (punch-through) to the drain.
The positive voltage applied to the sources (source lines) during erase reverse-biases the P-N junction formed at the N-type source diffusion of each cell and the P-type substrate. That reverse-bias voltage is the cause of undesirable cell-breakdown-voltage problems during flash erase. The cell-breakdown problem is sometimes referred to as the field-plate breakdown of the source to the substrate during erase. The same cell-breakdown problem occurs if a sufficiently large reverse voltage is applied to the drain diffusion.
U.S. Pat. No. 4,924,437 issued May 8, 1990, also assigned to Texas Instruments Incorporated, describes a Fowler-Nordheim method of programming a cell by applying a pulse of about xe2x88x928V to the control gate together with about +5V applied to the source. While in the majority of nonvolatile-memory-array types, erased cells have floating gates with a neutral or almost neutral charge, in that example erased cells have negatively charged floating gates.
A flash memory using negative wordline erase and triple-well CMOS technology is described in xe2x80x9cA 5-V-Only 16-Mb Flash Memory with Sector Erase Modexe2x80x9d by Toshikatsu Jinbo, et al., in Vol. 27, No. 11 of The Journal of Solid-State Circuits, November, 1992 at pages 1547-1553. The array described in that article has sources of xe2x80x9cH-typexe2x80x9d cells, sometimes called xe2x80x9cNORxe2x80x9d cells, (see FIG. 2 of the article) connected to a common node. Each xe2x80x9cH-typexe2x80x9d cell has a drain implant (see FIG. 3 of the article) for the purpose of lowering the voltage required for hot-carrier-injection programming. Manufacture of the cells described in the article requires extra masking steps that are unnecessary for constructing a usable nonvolatile memory with control logic circuitry using the minimum number of masking steps. xe2x80x9cH-typexe2x80x9d cells are relatively large when compared to the size of cells, such as xe2x80x9cX-typexe2x80x9d cells. xe2x80x9cX-typexe2x80x9d cells are described, for example, in U.S. Pat. No. 4,281,397 issued Jul. 28, 1981, also assigned to Texas Instruments Incorporated. In the past, xe2x80x9cX-typexe2x80x9d cells have been limited to use in ultraviolet-erasable EPROMs. However, one of the advantages of xe2x80x9cX-typexe2x80x9d nonvolatile cells is that such cells may be scaled down in size with ongoing improvements in lithographic and processing techniques.
U.S. Pat. No. 5,299,162 issued to Kim et al. on Mar. 29, 1994 describes erasing to negative-threshold-voltage of a selected NAND-type nonvolatile cell by applying 20V to the substrate, source and drain with 0V on the control gate.
There is a need for a nonvolatile-memory array/cell structure that is constructed simultaneously with logic circuitry on the same chip. Such a structure is, for example, useful for controlling data flow into and out of a large-capacity hard-disk drive. Other applications include combination microcontroller/data-storage devices such as electronic cameras, answering machines, and automatic control devices of all kinds. Preferably the cell structure of the memory should use a minimum amount of space, yet be scalable along with the logic structure to take advantage of smaller photolithographic geometries as those capabilities become available. The cell area should be as small as the very small area required by ultraviolet-erasable EPROM cells. In addition, the cell structure should eliminate the problem of field-plate breakdown during flash erase. For flexible application, the memory should be flash-erasable line-by-line using positive voltages.
The method of this invention includes forming a floating-gate cell, a line of such cells, or an array of such cells, in an isolated well. At the same time, high-voltage and low-voltage logic transistors are formed. As in the prior art, during an erasing operation the source of each memory cell to be erased is driven to a first positive voltage while the control gate is at reference voltage. Using the isolated-well of this invention, the drain and the channel of each cell is also driven to a voltage nearly equal to the first positive voltage by driving the isolated well a second positive voltage that is equal to the first positive voltage, thus eliminating the field-plate breakdown-voltage problem. Because there is no need for a diffused source-junction erase window under the floating gate, each floating-gate cell is a one-transistor cell having roughly the same area as that of an ultra-violet-erasable EPROM cell made using the same technology. Without the prior-art requirement for a separate tunnelling region near the source, a masking step and a phosphorus implant are eliminated. The structure of this invention is, for example, realized in an X-cell memory array that has the small size of an ultra-violet-erasable EPROM and that has manufacturing complexity slightly greater than that of an ultra-violet-erasable EPROM. The high-voltage P-channel transistors and low voltage N-channel transistors of a microcontroller are formed on the chip at the same time the memory cells are formed.
The nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors.
With the control gate and the integrated circuit substrate at 0V, the deep N-well allows application of a positive erasure voltage of perhaps +16V to the source/drain diffusions and the P-well of the nonvolatile memory array during erasure. Alternatively, with the substrate at 0V, a smaller positive erasure voltage (perhaps +12V) is applied to the source/drain diffusions and the P-well, and a negative erasure voltage (perhaps xe2x88x926V) is applied to the control gate. Application of those voltages permits the cells of the memory array to be erased without the causing field-plate stress at the p-n junctions between the source/drain diffusions and the P-well.
The term xe2x80x9cwellxe2x80x9d as used herein refers to a relatively large diffusion region formed in a semiconductor substrate. Such diffusion regions are sometimes referred to as xe2x80x9ctanksxe2x80x9d, xe2x80x9ctabsxe2x80x9d or xe2x80x9cmoatsxe2x80x9d. The xe2x80x9cwellsxe2x80x9d, xe2x80x9ctanksxe2x80x9d, xe2x80x9ctubsxe2x80x9d or xe2x80x9cmoatsxe2x80x9d are generally large enough to contain the diffusion regions and channels of active circuit elements.
The process results in a memory array with rows and columns of cells having a size and structure similar to those of a prior-art ultra-violet-erasable X-type arrays and includes high- and low-voltage logic circuitry on the same chip. The final device combines logic transistors and a memory with a dense flash EPROM circuitry, both formed with the manufacturing ease of that for an ultra-violet-erasable EPROM structure.